1. Field of the Invention
The present invention relates to a reconfigurable address generation circuit for image processing and to a reconfigurable LSI which comprises the same, and more particularly relates to an address generation circuit which, during image processing, generates read address for image data in a memory.
2. Description of the Related Art
A reconfigurable integrated circuit device (a LSI) comprises a plurality of processor elements and a network which connects between these processor elements, and the structure of the processor elements and the structure of the network between the processor elements can be set up into any arbitrary calculation state or arithmetic circuit, based on configuration data which a sequencer outputs in response to an external or an internal event.
A prior art type programmable microprocessor reads out commands stored in a memory in order and processes them sequentially. Accordingly, the commands which can be executed simultaneously by a single microprocessor are limited in number, and there is a limit to the processing capability.
In this connection, in a reconfigurable integrated circuit device, there are provided in advance a plurality of processor elements of a plurality of types such as logical arithmetic units (ALUs) which are endowed with the functions of adders, multipliers, comparators and the like, delay circuits, counters and so on; and, furthermore, a network is provided which connects between these processor elements, and the processor elements and network may be reconfigured to any desired structure, based on configuration data from a state transition control unit which includes a sequencer, and performs predetermined calculations in this calculation state. If a plurality of arithmetic circuits are configured by the plurality of processor elements, data processing may be performed in these arithmetic circuits simultaneously. And, when the data processing in one calculation state has been completed, another calculation state can be set up with a different set of configuration data, and different data processing can be performed in this state.
By being reconfigured to different calculation states dynamically in this manner, a reconfigurable integrated circuit device is able to enhance the data processing capability with respect to large volumes of data, and thus is able to enhance the overall processing efficiency. Such a reconfigurable integrated circuit device is, for example, described in Japanese Patent Laying Open Publication 2001-312481.
The above described reconfigurable LSI may be reconfigured dynamically to arithmetic circuits which have been optimized for various different types of data processing. Image processing is a representative one of these types of data processing. Filter processing such as smoothing processing or the like such as for example pixel data for 3×3 pixels, upon a single frame of bitmap image data, is included in such image processing. In this case, along with processing the subject pixels, calculation processing is performed upon the image data for the pixels surrounding them. Other types of image processing include processing upon the bitmap image data for a single frame in units of 8×8 pixels for extraction of high frequency components and low frequency components. Such processing is known to be performed in an MPEG decoder. In this extraction processing as well, calculation is performed upon the image data in pixel units having a plurality of rows and columns, and it requires the image data for the surrounding pixels.
In this type of image processing, the bitmap image data stored in an external memory is read out by predetermined blocks and is temporarily stored in an internal memory, and then this image data is read out from the internal memory and image processing is performed thereupon. In this case, the image data for the pixels surrounding the block is also stored in the internal memory, and the image data for a block which includes these surrounding pixels is read out; i.e., the image data including the surrounding pixels is read out by 3×3 pixel units or 5×5 pixel units or the like. In order to do this, a processor element which performs address generation for reading out image data from the internal memory is required.
However, when processing the image data for the pixels positioned on the left, right, top, and bottom edges of the frame, since no image data exists to the outside of the frame, therefore it is necessary to read out repeatedly the image data for the pixels which are positioned at the frame edge. Accordingly, it is required to generate a different address for being read out, according as to whether or not the pixel to be read out is one which is outside the frame. In other words, in the case of a pixel which is internal to the frame, an address is generated which simply corresponds to the pixel; while, in the case of a pixel which is outside the edge of the frame, an address is generated which, instead of corresponding to this pixel, corresponds to a pixel in an edge position.
However, when configuring a variant read out address generation circuit for the above described variant reading out operation by processor elements, the number of processor elements which are required is increased, and this is not desirable from the point of view of a reconfigurable LSI.